Based on WiMax and its derivatives in emerging broadband wireless standard protocol requires higher and higher throughput and data rate. These agreements made fast chip rate and digital radio processing program can use the FPGA hardware to achieve the best.
FPGA is very suitable Cooperation High-performance, cost-effective solutions to achieve these numbers in the physical layer protocol functions, as they include a wealth of resources:
1.DSP module can be used to achieve a variety of FIR filtering and FFT / IFFT operation of adders and multipliers required / accumulator functions;
2.SERDES transceiver, can support the wireless front-end and baseband digital board between the CPRI and OBSAI interface;
3. FPGA embedded RAM block important memory (EBR), can be used to store filter coefficients, perform block interleaving and FEC decoding to achieve (Turbo, Viterbi, Reed-Solomon, etc.);
4. Speed LVDSI / O, respectively, from the ADC and DAC support to a wide parallel interface. These converters are defined RF / analog functions and low-cost digital baseband logic between the boundaries. Interface, the higher the rate, low-cost FPGA solution that can integrate more statistics on the frequency / digital down conversion function.
This article focuses on the first resource that DSP multiplication module. Multiplication by reducing and optimizing DSP FFT and FIR in the module implementation, designers can minimize the use of resources to meet the throughput requirements under, allowing users to use the most cost-effective ready-made FPGA devices. The following four types of multipliers saving techniques in this introduction.
Functions for efficient complex multiplication WiMaxOFDM
WiMax system design, an important feature is to support orthogonal frequency division multiplexing (OFDM). FPGA makes use of IFFT and FFT, respectively in the discrete time realization of OFDM transmitter and receiver become particularly vulnerable. Such as 802.16a and other agreements require 256 samples of the FFT. The 802.16e The agreement calls for a variety of FFT samples, or the flexibility to adjust the FFT samples to meet the dynamic channel and bandwidth requirements (Extensible OFDMA).
Complex multiplication In the implementation of the FFT 256 and 1024 samples, the Radix-4 structure can be the most efficient use of multipliers. FFT Algorithm 4 samples by multiplex Discrete Fourier Transform (DFT) butterfly structure decomposition. For example, a 16-point FFT can be extracted by time, by taking or other related frequency decomposition method with two Radix-4DFT structure to achieve. Level 1 4 4 samples from the DFT composition, level 2 4 4 o’clock from the same DFT component. Since the output of each DFT requirements before the next level in the feed for the results presented provide three phases factors, so the first 1 and level 2 the phase factor between the needs of 9 9 complex multiplication.
First glance, the implementation of a complex multiplication requires four multipliers and two adder / subtractor. However, the expression can be re-written in another only three multipliers, three adders and two subtraction expression. It is noteworthy that the adder is the core logic in the FPGA implementation, using a rich bit by bit into bit mode (ripplemode) generic programmable logic unit (PLC) chip.
If D = Dr + jDi is the plural of data, C = Cr + jCi are complex coefficients, then the standard complex multiplication expression as follows:
E1: R = D * C = (Dr + jDi) * (Cr + jCi) = Rr + jRi (1)
Where Rr = Dr * Cr-Di * Ci, Ri = Dr * Ci + Di * Cr
These standards require the use of four multiplier expression. The expression can be re-order algebraic methods to:
E2: Rr = Dr * Cr-Di * Ci (2)
E3: Rr = Dr * Cr-Di * Ci +0 (3)
E4: Rr = Dr * Cr-Di * Ci + (Dr * Ci-Di * Cr) – (Dr * Ci-Di * Cr) (4)
E5: Rr = (Dr * Cr-Dr * Ci + Di * Cr-Di * Ci) + (Dr * Ci-Di * Cr) (5)
Complex expression is the result of the new:
E6: Rr = [(Dr + Di) * (Cr-Ci)] + (Dr * Ci-Di * Cr) (3 times multiplication) (6)
E7: Ri = Dr * Ci + Di * Cr (reuse the product from the Rr) (7)
Shown in Figure 1, the optimal complex multiplication can be three multipliers, three adders and two subtractor realized. It is noteworthy that, in the FPGA, the addition / subtraction module relative die area used is less than 18 Ã? 18 multiplier module.
Figure 1: The 4 and 3 multipliers of complex multiplication.
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